Detalles del proyecto
Descripción
Globalization of integrated circuit (IC) fabrication has resulted in opportunities for untrusted foundries to deliberately install backdoors, i.e., hardware Trojans, into cyber systems for an adversary to exploit at will. Reverse Engineering (RE) is the only approach in the hands of defenders that has the potential to guarantee trust. However, the existing RE workflow is ad-hoc, unscalable, error-prone, and requires manual intervention. In this project, I-C-U consists of technologies that assist in resolving these issues by developing critical algorithmic infrastructure and real-world data to advance automation in IC RE workflow. I-C-U also introduces measures to prevent the theft of intellectual property (IP) through misuse of RE and further enhances the capabilities of defenders by verifying the authenticity of their IC's design more efficiently. Finally, I-C-U also focuses on disseminating this knowledge through educational programs and transferring key RE-assisted hardware assurance technologies to the industry. These key developments enable the utilization of a competitive global supply chain while simultaneously enabling security and trust in the manufactured IC.
The tool suite, called I-C-U, systematically address the limitation of RE by formalizing the workflow through (1) Automation of the RE workflow including fault-tolerant Scanning Electron Microscopy (SEM) image acquisition, segmentation, and gate-level netlist generation; (2) Creation of resources to support the development of data/AI-driven design recovery approaches via generation of synthetic images from real-world data, models that capture the noise introduced by IC sample preparation, de-processing, and SEM imaging, and use of privacy-preserving transforms; (3) Development of risk analysis metrics for evaluating design recovery and using them to deploy countermeasures during the physical design process that inhibit the attacker's ability to perform RE and/or promote a defender's ability to detect IP infringement and hardware Trojans. These objectives, when aggregated, satisfy the primary goal of advancing automation in IC RE workflows while protecting critical semiconductor IP.
This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
Estado | Activo |
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Fecha de inicio/Fecha fin | 1/4/22 → 31/3/25 |
Enlaces | https://www.nsf.gov/awardsearch/showAward?AWD_ID=2131480 |
Financiación
- National Science Foundation: USD1,199,042.00
!!!ASJC Scopus Subject Areas
- Seguridad, riesgos, fiabilidad y calidad
- Materiales electrónicos, ópticos y magnéticos
- Redes de ordenadores y comunicaciones