CSR:Small:Efficient and Predictable Memory Hierarchies for High-Performance Embedded Systems

0915503

CSR:Small:Efficient and Predictable Memory Hierarchies for High-Performance Embedded Systems

Abstract

High-end embedded systems are increasingly used for complex computation, such as advanced image processing and speech processing. Such complex tasks often involve irregular data structures such as linked data structures, or exhibit irregular access patterns even with regular data structures. Managing scratchpad memory for such tasks becomes increasingly challenging due to the difficulty of determining addresses that will be accessed in the future. For such complex applications, hardware-managed storage (caches) can perform relatively well without much programming effort. However,caches do not offer predictability required to derive a tight worst case execution time (WCET) bound in real-time systems, due to their dynamic behavior that is difficult to predict at compile time.

The goal of the project is to explore a new intelligent real-time cache, which offers ease of storage management as well as allows programs to control caching behavior with low overheads, providing predictability that supports real time analysis. The work consists of: (1) Instruction and architecture support that provides primitives to control cache behavior with low overheads, (2)Development compile-time analysis and run-time support to support the new cache, and (3)Proof-of-concept of the proposed system.

Improved memory performance and predictability will be to make computer systems more efficient, enable more challenging problems to be solved, and improve energy-efficiency of existing applications. This project will also extend outreach to undergraduate and high-school students about the value of engineering to society and attract more students into the field. It will also benefit the public by disseminating research results through publications and tool releases.