A Comprehensive Framework for Soft Real-Time Multicore Applications Motivated by Safety-Critical DoD Systems

Multicore processors provide significant computational capacity within a restricted size, weight, and power (SWaP) envelope. As such, they are seen by many people as a key enabler for a wealth of new computationally intensive safety-critical embedded systems. However, safety-critical systems must be certified before being deployed, and certification procedures applicable to multicore equipped safety-critical systems are currently lacking. Motivated by this need, the Army, Navy, and Air Force are currently involved in a joint initiative to devise such procedures. As part of this initiative, the development of methods for supporting soft real-time (SRT) application components, which can tolerate some deadline violations, has been identified as a pressing need. While it may seem that safety-critical applications would necessarily be composed of only hard real-time (HRT) components, which can never miss deadlines, this is in fact not the case. Indeed, looking forward, the computational capacity of multicore machines will be most needed in embedded applications that provide some degree of functional autonomy. As research on this topic moves forward, we will see ever more sophisticated systems endowed with increasingly advanced ÒthinkingÓ capabilities that carry out decision-making and planning functions. Given their highly dynamic nature, these capabilities will almost certainly be realized via system components that are SRT. As for the current embedded-computing landscape, DoD researchers involved in the joint initiative mentioned above have claimed that nearly all safety-critical DoD applications today have components that are SRT. Driven by these observations, this project is directed at developing a comprehensive framework for supporting SRT workloads on multicore machines. This framework will enable various metrics for defining SRT correctness to be used by application designers. In developing the proposed framework, fundamental questions regarding the scheduling of SRT workloads on multicore machines and the validation of their timing constraints will be resolved. This project will build upon significant prior work by the PI that pioneered tardiness bounds as a useful metric for SRT correctness in multiprocessor systems. The key outcomes of this project will be: (i) new tardiness analysis for multiprocessor systems with asymmetriesÑsuch asymmetries are becoming increasingly common in safety-critical application domains, due to both hardware heterogeneity and the manner in which hardware (heterogeneous or not) is shared by disparate applications; (ii) techniques for supporting notions of SRT correctness that require that a specified fraction of deadlines be metÑthis work will greatly expand the range of SRT metrics afforded to system designers; (iii) new scheduling approaches that lower tardiness by increasing intra-task parallelismÑthis work will be used as a basis for constructing a single framework that encompasses all of the studied SRT metrics; and (iv) an experimental evaluation of this framework and the SRT-related tradeoffs it exposesÑplanned experiments will include case-study evaluations defined through ongoing interactions with colleagues at DoD agencies and in the defense industry.