SHF: Small: Improving Memory Performance on Fused Architectures through Compiler and Runtime Innovations

During the past decade, accelerators such as Graphics Processing Units (GPUs) have entered the area of general-purpose computing. They are now widely used for achieving high performance in scientific simulation, business analytics, image processing, and many other application domains. Their effectiveness however has been largely constrained by narrow and slow interconnections to multicore CPUs. Instead of such disjoint memories for multicore CPUs on one side and GPUs on the other, contemporary architectures are adopting an integrated design: Conventional CPUs and co-accelerators are integrated on the same die with access to the same memory. The integration provides new opportunities for synergistic execution on CPUs and GPUs, but can also intensify resource contention within the memory hierarchy. The implications yet remain to be understood.

This project aims to systematically explore the new challenges and opportunities of the integration, especially for compilers and runtime systems in governing program transformations and maintaining them at runtime for data locality, task partitioning and scheduling. The PIs propose to advance the state of the art by promoting synergistic execution in support of data sharing while creating spheres of isolation between CPU and GPU execution to mitigate resource contention of non-shared data. The proposed techniques include a set of novel compiler transformations, concurrent program control and data abstractions, and systems mechanisms that foster

sharing and reduce cross-boundary contention depending on memory access patterns with respect to shared hardware resources. This synergy between compiler techniques and the runtime system has the potential to significantly improve performance and power guarantees for co-scheduling program fragments on fused architectures.