SHF: Small: AnyCore: A Universal Superscalar Core

Future microprocessors will contain many processing cores. This future presents a unique opportunity to increase performance and decrease power consumption by providing different core types, each optimized for different instruction-level behavior within and across applications. The questions of how many core types, how many of each type, and what should each type look like, are perplexing in the face of arbitrary run-time scenarios. This is because (1) Instruction-level behavior is infinitely diverse whereas the number of core designs that can be practically included is limited; (2) Parallel applications tend to favor homogeneous cores for their uniform tasks. Yet, the optimal homogeneous multi-core processor differs for different parallel applications, which are not static; (3) Multiprogrammed workloads tend to favor heterogeneous cores to match their diverse tasks. Yet, the optimal heterogeneous multi-core processor depends on the mixture of tasks and their arrival rates to the system, factors which vary over time; and (4) Even if we consider a fixed run-time scenario, the optimal configuration of core designs depends on latency, throughput, and power preferences. All of these factors vary over time. Thus, while the multi-core era makes it possible and desirable to provide many core types, it is nearly impossible to determine which ones and how many of each.

This project proposes AnyCore, a comprehensively reconfigurable superscalar processing core. AnyCore has a unique and ambitious objective: each one of its hundreds of configurations, called 'virtually fabricated cores', should achieve the same frequency, cycle-level performance, and power as explicitly designing and fabricating just that core. A novel multi-core architecture comprised of many replicated AnyCores can be configured into arbitrary heterogeneous and homogeneous multi-core designs, each having the performance and power of a fixed design. This will enable achieving optimal latency, throughput, and power targets for arbitrary workload types and arbitrary instruction-level behavior within their constituent tasks. The research could have potentially significant impact on the design process of future commercial processors, as well as on education and research as a rapid simulation platform.