SaTC: CORE: Small: Towards Smart and Secure Non Volatile Memory

Non-volatile memory (NVM) technologies and the 3D-integration technology reshape memory systems. Although providing many desirable features such as low leakage power and fast system restart, the non-volatility of NVM introduces the vulnerability to data remanence attacks. This project leverages the processing-in-memory (PIM), enabled by vertically stacked 3D integration of integrated circuits, to overcome the security challenge associated with NVM.

In this project, we use an attack model, in which an attacker can physically obtain the NVM chip and scan the data stored in NVM, can also snoop on the memory bus to retrieve data and addresses; and can tamper with the memory content as well as commands. Our trust base includes both the processor and the memory chip, meaning that the hardware logic and state registers inside the chips are well hidden from the attacker. To protect against data scanning and memory bus snooping, we utilize counter-mode encryption to encrypt data and obfuscate addresses. The data stored in NVM are always encrypted while the addresses are encrypted at the processor side and decrypted at the memory side. The decryption logic becomes a part of the PIM logic on NVM chips. To protect against data tampering, we develop efficient integrity checks by re-purposing error correction codes (ECC) for integrity checking such that the existing error correction logic can be used for both error detection/correction and integrity verification. Overall, we leverage PIM to protect data and access patterns and ensure the data integrity. The end result of the project is smart and secure NVM architecture designs.