II-NEW: Implementation of an Architecture Simulation Platform with a Virtualized Real-time Operating System Interface for Kilocore-scale Heterogeneous Embedded Chip MultiProcessors

Portable embedded systems place ever-increasing demands on high-performance, low-power microprocessor design. This has triggered a paradigm shift in the embedded processor industry, and embedded processor architects are permanently altering their roadmap to incorporate multiple cores on the same chip to preserve exponential computational speed-up (to continue Moore's law). While the industry focus is on putting higher number of cores on a single chip, the key challenge is to optimally architect these processors to meet stringent real-time constraints in virtualized environments with different real-time operating systems (RTOS). Moreover, these processors will work on diverse application types having sporadic event-driven data. In such complex systems, the optimal performance can only be realized by co-designing the RTOS kernels, the virtualization environment, and the processor micro-architecture.

The goal of this research is to develop a cycle-accurate simulation platform for the micro-architectural exploration of future kilocore-scale heterogeneous embedded chip-multiprocessors (ECMPs), together with an interface to boot RTOS-es on the simulator, and enable virtualization on the ECMPs. The integrated framework is flexible and modular for designing a wide variety of ECMPs and RTOS-es, flexibly threaded for fast simulation of thousands of cores on a wide range of computing platforms, assertion-based and check-pointed for quickly regenerating and changing complex trigger conditions required for debugging, instantly-bootable to reduce the RTOS booting time from power-up to simulation, enabled with deep-chip-vision for better observability of silicon behavior at the architectural level, and open-sourced for non-commercial use. The RTOS integration environment provides software interfaces and libraries to the architect and the OS designer to simulate the execution of embedded applications on different exploratory ECMPs, in the presence of different virtualization scenarios and RTOS scheduling algorithms. This project promotes inter-disciplinary research between computer architects, RTOS designers, Computer-Aided Designers, and embedded application programmers at different universities and research institutions. The various education components woven into the project will foster team-based research, learning, and teaching among the university student participants.