An FPGA Testbed for Characterizing and Mapping DOD Applications

The widespread use of unmanned autonomous surveillance systems in military operations offers significant advanced new capability while simultaneously introducing complex challenges in the rapid development/deployment and testing of these systems. Current payloads for these systems have stringent constraints with respect to their maximum weight, power consumption, processing speed, sensor types, interface requirements, and overall cost. The traditional approach to the design of these payloads involves repeated system level engineering design steps identifying on-board computers and application specific boards, each supplied by a specific manufacturer. This approach results in systems with closed or highly proprietary architectures that have a very limited potential for reuse. While each board typically enables a particular function for the payload, the problem of meeting payload design specifications is exacerbated by the need to identify manufacturers with interfaces that match the sensors. Hence, for each new system, there is typically at least one complete redesign to meet the dynamic nature of advances in sensor technology. The solution to many of these issues is to use Field Programmable Gate Arrays (FPGAs) in conjunction with on-board processors as a platform to develop a Context Neutral Payload (CNP) that supports a myriad of sensor types, meets size and weight constraints, provides superior processing power, can serve a dual role as a ground station, and can reduce the data requirements for communication of sensor data to satellites/ground stations. Reconfigurable Computing (RC) systems combine onboard processors with FPGAs to offer programmable hardware systems that can be reloaded for disparate applications while offering 1-2 orders of magnitude speedup. This proposal involves the basic research required for the development and implementation of a context neutral payload (CNP). The CNP can be reused in various unmanned vehicles (air, ground, or sea) with a wide range of sensors. More specifically, this proposal attempts to leverage the previous work to develop a Remote And Reconfigurable Computing Environment (RARE) while addressing the problem of porting High Performance Computing (HPC) applications directly to FPGA-based architectures. Accordingly, the objectives of the proposed research are to: develop a comprehensive floating point library of essential functions for military applications; demonstrate order of magnitude speedup of reconfigurable computing applications; and train students in the use of RARE tools for rapid military application development. As an outcome of this research, the institution will be able to demonstrate 10-100X speedup of various HPC algorithms using its novel patented architecture. The institution will develop a RARE resource that can be accessed from a remote site. Experiments conducted by RARE researchers will continue to verify that REMOTEHARDWARE versions of specific computation-intensive algorithms can complete execution significantly faster than LOCAL SOFTWARE versions of the same algorithm. In addition, students will be introduced to research conducted as a part of this grant and encouraged to pursue careers in engineering positions throughout the DOD.